The digital silicon photomultiplier — System architecture and performance evaluation

In this paper we present the first fully digital implementation of the Silicon Photomultiplier. The chip design is based on the technology demonstrator chip presented in. The new sensor represents a self-contained detector including a JTAG controller for configuration and test, single-ended and differential clock and test input signals, an integrated acquisition controller and two serial data outputs. The sensor is based on a single photon avalanche photodiode (SPAD) technology integrated in a standard CMOS process flow. Photons are detected directly by sensing the voltage at the SPAD terminal using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective activation of individual detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the two integrated time-to-digital converters. Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The resulting data packets are transferred to the readout system through a serial data interface. In this paper, we discuss the new sensor architecture and evaluate its performance.