Exploiting component/event-level parallelism in concurrent fault and design error simulation

The paper describes the algorithm CON/sup 2/FERS, which exploits the event level and component level parallelisms in the concurrent technique for fault and design error simulation. This algorithm assumes asynchronous, message based operation with NORMA, and MIMD models of programming. A design verification tool based on this algorithm is developed with object oriented methodology using C++ and PVM. This implementation is executable on any Network of Workstations (NOW) and/or any general purpose parallel machine. The statistics on fault and error simulation performance and load balancing for some benchmark circuits are presented. Various experimental results of the effect of network and load on the performance of the CON/sup 2/FERS, and the applicability of the algorithm for the hardware acceleration of CFES are also presented.