Implementation of a charge-based neural Euclidean classifier for a 3-bit flash analog-to-digital converter

This paper describes the implementation of a Euclidean squared classifier with a charge based synaptic matrix and discriminator, based on a previously implemented Hamming classifier. The discriminator circuit is a generalized n-port version of the two-port differential charge-sensing amplifier that is conventionally used in DRAM's for bitline sensing. Both the quantifier and discriminator are implemented by charge based techniques, granting the simultaneous availability of high integration density, low power consumption, and high speed. The analog-to-digital (A/D) implementation was chosen to illustrate the network's classification characteristics, since A/D conversion can be interpreted as classifying an input in terms of A/D quantization levels. A detailed analysis of the classifier configuration is presented. Design issues are addressed at both the system and circuit levels, and some limitations are identified. Both simulation results and measurements of the implemented chip are presented to confirm the theoretical analysis. The circuit occupies an area of 500 /spl mu/m/spl times/250 /spl mu/m, operates with a single 5 V power supply, and consumes less than 1 mW of static power.