An embedded DRAM module using a dual sense amplifier architecture in a logic process

A dual sense amplifier array architecture (DSSA) amenable to a logic-process-compatible 1T DRAM eliminates the penalty that can be imposed by any two-bank-architecture-based DRAM. A 32k/spl times/16 eDRAM test chip is used to verify the architecture. The chip is implemented in a 0.5 /spl mu/m single-poly, triple-metal CMOS process. The DRAM array cell capacitance and bitline parasitic capacitance are 23 fF and 550 fF, respectively. The DRAM cell is 33 /spl mu/m/sup 2/ (7.38/spl times/4.5 /spl mu/m/sup 2/).