Implementation of static DSP algorithms using multiplexed PEs

An efficient and flexible ASIC implementation method suited for static DSP algorithms is presented. It is aimed at low power implementations with moderate speed requirements. The method allows for the processing elements to be multiplexed in order to reduce the amount of resources required. A method to find a minimal number of resources and a corresponding architecture from the cyclic scheduling formulation is described. An implementation of a wave digital bandpass filter is used as an example. The low power consumption and high resource utilization is obtained by using the cyclic scheduling formulation that leads to a maximally fast implementation. The excess speed can be converted to low power consumption by reducing the power supply voltage.