High throughput systolic memory architecture using three directional dataflows

This paper describes a new scalable systolic memory architecture. It provides low initial latency and high throughput using three directional systolic dataflows. The throughput is determined not by the entire memory size of designed chip but by the size of a single submemory block element. Pipelined address decoding reduced the access time of a single sub-memory block. It supports scalability by regular operations of all elements. We designed 4k-bit sized prototype which operates at 77 Mhz.