Device degradation due to stud bumping above the MOSFET region and the effect of annealing on the degradation

This paper presents the effect of stud bumping above the MOSFET region on device degradation. Stud bumping above the MOSFET region generates an interface trap at the Si/SiO/sub 2/ interface and results in the degradation of mutual conductance for the N-channel MOSFET. The interface traps induced by stud bumping are apparently eliminated by both N/sub 2/ and H/sub 2/ annealing. However, the hot-carrier tolerance of H/sub 2/ annealing is one order of magnitude stronger than that of N/sub 2/ annealing. This effect is explained by terminating dangling bonds with hydrogen atoms.