Electrical characteristics of wedge-shaped gate-oxide in recessed-LOCOS

An analytical solution of the electric potential and field for the wedge-shaped gate-oxide, which is formed inevitably in recessed-LOCOS structure, is proposed. This abnormal geometry includes an apex, which brings about an electrical failure during the gate-bias test. First, we show that the apex angles change according to the thickness of the sidewall nitride spacer by process simulation and physical arguments. We model the wedge-shaped gate-oxide in a simple geometry and calculate the electric potential and field with the various apex angles. We calculate the resultant tunneling current using the Fowler-Nordheim model. As the result of the calculation, we prove that above a certain spacer thickness, the breakdown voltage fluctuates from site to site within a wafer in gate-bias test with the memory cell array pattern. We predict that this breakdown phenomenon occurs regardless of the gate-oxide thickness and also suggest the presence of the limiting apex angle to maintain the gate-oxide reliability.