Design of high-performance massively parallel architectures under pin limitations and non-uniform propagation delay

Intermodule bandwidth is one of the major constraints on the performance of current and future parallel systems. We propose and evaluate several high performance bus based parallel architectures, including bus based cyclic networks (BCNs) and quotient cyclic networks (BQCNs), which are particularly efficient in view of their respective intermodule communication patterns. The intercluster connection in a BCN is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degree of a basic BCN is 3, while those of BQCNs and enhanced BCNs can vary from a small constant (e.g., 2) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. A variety of algorithms can be performed efficiently on these networks, thus providing the versatility of BCNs and BQCNs.