Performance implications of the PowerPC architecture's hashed page table utilization in Windows NT

Windows NT/sup TM/ is a portable operating system, and as such has an abstracted view of the underlying processor architecture. One of the most processor-specific portions of an operating system is the management of virtual memory, and NT is no different in this respect. NT abstracts the processor-specific address translation mechanism and manages it as a translation lookaside buffer (TLB). This paper examines the performance ramifications of this abstraction when using the hashed page table (HTAB) on the PowerPC/sup TM1/ architecture.