A BiCMOS read channel two-chip combo for magneto-optical disk drives

A read channel two-chip processor for rewritable 3.5" magneto-optical disk drives is presented. The front-end includes an automatic gain control (AGC) circuit, a programmable 6-pole 2-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer and a data synchronizer with 3:1 operating range to support a constant density recording with 8-24 Mbit/s data rate in 2,7 RLL format. The architecture of the chip provides a high degree of programmability through a serial microprocessor interface, fast switching (<1 /spl mu/s) between sector mark and data modes, and four levels of power management in a 1.5 /spl mu/m 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode.