Testability controlled physical design of vertically stacked integrated circuits

Vertical integration technology is expected to provide several advantages, such as high packaging density, parallel processing, high speed operation and an improved reliability. Basic design aspects for vertically stacked integrated circuits are discussed in this paper. A novel partitioning method for vertically stacked integrated circuits (VIC) will be proposed which generates testable circuit partitions. Generated circuit layouts of partitioned MCNC benchmark circuits demonstrate the superiority of 3-D circuit layouts over planar circuit layouts especially for increased circuit sizes.