Performance driven placement for cell-based designs

In this paper we present a performance driven quadratic programming based placement method for large ASICs. A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing driven placement for cell based layouts. The bounds, if satisfied, guarantee correct operation of circuit for specified timing requirements. The approach has been integrated with high-level synthesis tools for generating layouts of datapaths of synthesized designs.