Techniques for reducing switching noise in high speed digital systems

Simultaneous switching noise (SSN) caused by parasitic inductance in the power supply distribution network is a severe problem in high speed digital circuits and systems. The influence of SSN, negligible when rise/fall time is long (>5 ns), becomes an important factor, limiting circuit performance in the sub-nanosecond rise time region. This paper presents simulation results of SSN in high speed digital systems. Technical solutions for reducing SSN in the light of current developments of advanced packaging and assembly technologies are discussed. A quantitative comparison of SSN in digital systems implemented with conventional as well as advanced assembly techniques is given.