Characteristics of interconnect delay in 0.5 micron CMOS

Accurate analysis of the interconnect is imperative in contemporary sub-micron geometry circuits. The drive characteristics of the driving transistor play a significant role in the response of the interconnect. This paper presents a detailed analysis of a capacitively loaded distributed RLC system driven by a transistor. Using an analytic model the performance of the interconnect will be characterized with respect to design and technology parameters of a CMOS process technology with L/sub eff/=0.45 micron.