Deration of power dissipated in ASICs with temperature, process, and voltage variations

This paper presents a method to accurately derate power dissipated in ICs as temperature, process, and voltage are varied from the baseline conditions. Our cell-based power consumption model accounts for the waveform slope effects at the input of a gate, its output load, and logical state-dependencies, in terms of pre-characterized power coefficients. We further generalize this model to specify the temperature, process, and voltage sensitivities of each power coefficient. A representative subset of the library cells is first characterized at conditions varying from the baseline conditions. Since the standard deviation of scaling factors for each power coefficient is found to be within tolerance limits, for the remaining cells in that library we postulate the power deration factors based on the computed scaling factors. Results of our extensive power deration study for different logic cells verify our postulation. The power predicted by our method is within 5% of Spice results for temperature and voltage variations, and within 12% for process variations.