Teaching digital system design using VHDL

This paper describes how VHDL may be used in teaching a senior course in digital systems design. The acronym VHDL stands for VHSIC Hardware Description Language. VHDL is a general-purpose language which can be used to describe and simulate the operation of a wide variety of digital systems ranging in complexity from a few gates to an interconnection of many complex integrated circuits. VHDL was originally developed for the military to allow a uniform method for specifying digital systems. VHDL has since become an IEEE standard and it is becoming widely used in industry in the United States as well as in Europe.