OLIVIA: object oriented logic simulation implementing the VITAL standard

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates back-annotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulation performance at gate level by allowing only a restricted set of VHDL. In this paper, we present an efficient implementation of the VITAL-Standard in our object-oriented, event-driven logic simulation tool OLIVIA. First promising results concerning simulation performance compared to conventional VHDL-Simulators are given.