The buck stops with wafer test: Dream or reality?

Summary form only given. In the industry today, testing packaged chips achieves the outgoing DPPM (defective parts per million) requirements. Usually, functional and structural test patterns are used at wafer sort, followed by functional/structural testing with packaged parts, and then by functional system level testing, each subsequent stage significantly more expensive than the previous one. By and large, wafer test have not been used for performance binning and reliability screening. Also, packaged parts are tested in burn-in chambers and on load boards, using either the same structural patterns used at wafer sort or with functional test patterns. As design complexity has gone up significantly over the past decade, the test cost has grown disproportionately. If a die is found to be faulty at a stage after wafer sort, then the design house incurs the cost of packaging, and for subsequent testing. In one business model, the fabless design house buys dies from the foundry that pass wafer sort, and needlessly pays for dies that are later found to be bad after packaging. Furthermore, this problem can be severe for dies that go into multi-chip modules or stacked ICs, as all the dies in the packaged chip have to be thrown away even if one constituent die is found to be bad. Since it is increasingly more expensive to test chips down-stream (using functional testers or on a system) and since there is downward pressure on product costs with the advent of inexpensive SoCs, it becomes important to achieve maximum test quality in terms of defectivity and binning, at wafer sort. Known good die (KGD) refers to dies which have been tested to the same quality and reliability levels as their packaged counterparts. Even though the KGD problem has been discussed since the mid 90's, the problem becomes more and more difficult with every new process node and new design requirement. There is need to develop high quality tests, on die DFX instrumentation, and reliability screens that can be applied at wafer sort, given pin constraints. In addition to addressing failure mechanisms of a bare die, such as gross defects, small delay defects, cross-talk, and variations due to photolithography, a good wafer sort test methodology and associated tests should not only be enough to reject bad bare dies, but also characterize the dies enough to enable estimation of the performance/power of packaged parts on a system.