An all-digital on-chip jitter measurement circuit in 65nm CMOS technology

An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a vernier ring oscillator (VRO) is used as a time-to-digital converter (TDC) to quantize the jitter information into digital codes. The proposed self-referred architecture with a cycle-controlled delay line doesn't require an external reference clock to measure the jitter of the on-chip signals. Therefore, the BIJM circuit design complexity is greatly reduced by the proposed architecture. The proposed all-digital BIJM is implemented in a 65nm CMOS process, and the input frequency range is 100MHz to 300MHz.