A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates 415K logic gates and 682Kbits embeded SRAM in 65nm single-poly seven-metal CMOS process with area of 2.47mm
²
. AVS video decoding of full 1920×1088 high-definition sequences at 60 frames per second is achieved at 166MHz clock frequency with power dissipation of 41.3mW at 1.0V supply voltage.