FPGA implementation of a chaotic oscillator using RK4 method

The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices. For digital realizations the Ordinary Differential Equations (ODE's) are replaced by a discrete time system. Furthermore numerical values are expressed in a numerical representation. It is well known that these two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we considered the use of the Euler's algorithm in two different numerical representations: (a) integer arithmetics and (b) single floating point IEEE-754 standard. For applications that require a good agreement between the analog chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be used. Guided by numerical simulations, in this paper we propose an improvement replacing the Euler's algorithm by the fourth order Runge Kutta algorithm (RKA). In order to diminish the required hardware a method based on blocks' reusing is proposed. The procedure is exemplified on a Lorenz CS. The whole design was implemented onto a FPGA EP3C120F7 by Altera^©, using only 12 % of its logic elements, 13% of its embedded multipliers and 34 % of its memory bits. The smallest Ciclone III device where our design fits is the EP3CA0UA8AI7.