An efficient VLSI architecture for template matching based on moment preserving pattern matching

In this paper, we describe the design of an efficient VLSI architecture for image template matching. The hardware algorithm and architecture for template matching are based on a technique known as moment preserving pattern matching, which is proposed by Chon-Chen (1990). The architecture fully utilizes the principles of parallelism and pipelining in order to obtain high speed and throughput. The proposed VLSI system is much simpler, achieves higher speed, has a lower hardware complexity and utilizes lesser memory than other hardware architectures proposed for template matching in the literature.