Low level image processing operators on FPGA: implementation examples and performance evaluation

This work deals with evaluation of hardware implementations of image processing algorithms for real time applications, using SRAM based field-programmable gate arrays. We discuss a generic architectural model adapted to this domain and to the technology characteristics. A method to evaluate the area costs and timing performances of architectures implemented on such a model is presented. A feasibility study of a pre-processing chain in an image-recognition system is presented.