A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-
$\mu{\hbox{m}}$
1P4M process with pixel pitch of 2.25
$\mu{\hbox{m}}$
. The designed 10-bit ADC dissipates only 90
$\mu\hbox{W/channel}$
with 1.5 V supply. The measured DNL and INL are
$+$
0.59/
$-$
0.83 LSB and
$+$
2.8/
$-$
3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.