An automated design methodology for yield aware analog circuit synthesis in submicron technology

This paper presents a new fully automated design methodology for analog circuit synthesis in submicron technology. It requires circuit topology and desired circuit performance as input and it produces not only the sized netlist but also the layout of the sized components. Today's submicron technology accompanies appreciable process variation. In conventional equation based circuit sizing technique there is high chance that the optimized design point is at the boundary of the feasible design space. Due to process variation the design point may fall outside the feasible design space and some of the specifications are not meet after fabrication, resulting poor yield. Our intention is to formulate a computationally inexpensive design centering technique to circumvent this yield problem in design. Analog designs are sensitive to its layout. Though in simulation any device dimension is possible but while doing layout, designers need to bring the design conforming to technology grid point. For better matching and to reduce process variation designers do common centroid layout for some special transistor pairs (differential pair, mirroring transistor etc.). Those layout related issues are considered in design phase and we produce device dimension with which direct layout is possible. Layout components are generated automatically through pcell by cadence SKILL.