High-Performance Poly-Si Vertical Nanowire Thin-Film Transistor and the Inverter Demonstration

In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both N- and P-TFT devices (with gate length down to 100 nm and a wire diameter of
$\sim$
30 nm) exhibit good transistor performance, e.g., high
$I_{\rm on}/I_{\rm off}$
ratio of
$> \hbox{10}^{6}$
, low subthreshold slope
$(SS \sim \hbox{100}\ \hbox{mV/dec})$
, and reasonable drain-induced barrier lowering [(DIBL);
$\sim$
50 mV/V] with a wire diameter of
$\sim$
30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.