Behavior of triple gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple gate FinFETs. The threshold voltage, subthreshold swing, transconductance, conductance, resistance and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. The results indicate that the DTMOS FinFET structure shows superior characteristics and a larger transistor efficiency, which is desirable for high performance low-power/low-voltage applications.