A combined channel and hardware noise resilient Viterbi decoder

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library.