Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm/sup 2/ fabricated in a 0.8 /spl mu/m CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.