A 150 MHz wave-pipelined adaptive digital filter in 2 /spl mu/m CMOS

Adaptive filters have often been implemented using the conventional least mean squares (LMS) algorithm due to its inherent simplicity and robustness. However, its poor pipelinability greatly limits its use as a high-performance filter. In this paper, we present a wave-pipelined delayed LMS filter architecture using advanced retiming methods and algorithm modification. In addition to the arbitrarily high-sampling rate that is possible due to the delayed coefficient adaptation algorithm, we retime the signal-flow graph (SFG) of a proposed architecture in order to accommodate wave pipelining of the multiply-and-accumulate (MAC) block. The trade-off for reduced cycle time is an increase in the filter's convergence time. The resulting systolic array implementation is highly pipelined for high-performance and is architecturally scalable because the sample rate is independent of the number of taps.