IEEE 1500 compliant test wrapper generation tool for VHDL models

This paper presents a method of automated test wrapper generation implemented in new CAD tool “Boundary Scan Generator”. The tool can be used for generating IEEE 1500 compliant test wrappers and corresponding CTL-programs from VHDL descriptions of integrated circuits. The tool is designed as cross-platform and extendable development environment, based on open interfaces and modular architecture.