A 57–66 GHz medium power amplifier in 65-nm CMOS technology

This paper presents the design and measurement results of a 57-66 GHz medium power amplifier in 65-nm LP CMOS process. This amplifier is designed with broadband matching concern, which can achieve a measured gain more than 21 dB from 57-66 GHz and have a 3-dB bandwidth more than 14 GHz while consuming 54 mW from a 1.2 V supply. The measured results exhibit P
_sat
of 10.3 dBm, P
_1dB
of 6.2 dBm, and the peak PAE is 16 %at 58 GHz. The chip size is only 0.3 mm
²
.