Electron Trapping in HfAlO High-$\kappa$ Stack for Flash Memory Applications: An Origin of $V_{\rm th}$ Window Closure During Cycling Operations

Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-κ materials. It is observed in this paper that the electron trapping in high-κ layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-κ layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming.