100 MHz serial access architecture for 4 Mb field memory

An architecture that improves serial I/O operation speed, reduces layout area, and permits simple control is presented. The architecture features a high-speed, simple configuration, an easy controllable data shifter, and an high-speed redundancy circuit. With this architecture, a 4-Mb field memory with 100-MHz serial access capability has been developed. The process technology used is 1.0 μm CMOS, and the die size is 12.94 mm×25.9 mm. The data register circuit area of the prototype chip was 40% smaller than that of conventional chips