A performance model for ATM switches with internal speedup

In this paper we study a non-blocking ATM switch with internal speedup. Modifying the model in Cao (1995), we can obtain the maximum throughput of the switch; approximating the output process by a discrete-time Markov modulated process, we can calculate the cell loss probabilities at the output buffers. In our approach, the incoming traffic is considered to have correlated destinations and asymmetric routing probabilities. Simulation results illustrate that the approach is very accurate.