Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (V
_th
) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO
₂
at the edge regions along the channel length/width directions and that a negative V
_th
shift is derived from hole trapping in the gate insulator far from the SiO
₂
/HIZO interface.