A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation

This paper investigates the adoption of LC-VCO to replace ring VCO for ultra-low-voltage sub-picosecond jitter clock generation in future 0.5-V LSI and power aware LSI. A 0.5-V LC-VCO using E-TSPC frequency divider with forward body bias technique is proposed and implemented. Significant performances, in terms of 0.6-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub-1mW P
_DC
, have been achieved in the measurement results.