System-level modeling of a Reconfigurable System on Chip for wireless sensor networks applications

This paper presents the system-level modeling of a Reconfigurable System on Chip (RSoC) that is being currently developed in our institution. Although there is a wide range of possible applications, our system is initially aiming fruit monitoring system. The proposed RSoC contains a 32-bit RISC microprocessor, reconfigurable structures, analog and digital interfaces, an RF transceiver and an Active Pixel Sensor (APS) matrix whose function will consist basically on image acquisition. The modeling at a high level of abstraction has been used lately in the design and verification of SoCs due to the rising complexity of such systems. Virtual platforms using SystemC description language at Transaction-Level Modeling (TLM) allow efficient simulations including software and hardware. In this work, a preliminary evaluation of a system-level description of the RSoC is carried out. A JPEG compression algorithm was mapped and implemented as a case study to test the accuracy of the model. Future implementations will include the description of an RF transceiver and the communication between two RSoCs.