Modeling Energy-Time Trade-Offs in VLSI Computation

The performance of today's computers is limited primarily by power consumption rather than the number of instructions executed. Because the energy required to perform an operation using VLSI circuits drops rapidly with the time allowed for the operation, many slow processors can complete a parallel computation using less time and less energy than a fast uniprocessor that can execute the best sequential algorithm. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose a simple model for analyzing algorithms that reflects the energy-time trade-offs of CMOS circuits. Using this model, we derive lower bounds for the energy-constrained execution time of sorting, addition, and multiplication, each with bitwise inputs, and we present algorithms that meet these bounds. These lower bounds are based on the energy-time costs of communication distance, rather than bisectional bandwidth arguments typical of area-time lower bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth. This work establishes a tractable method for the evaluation of parallel computations in a power-constrained environment.