Good Endurance and Memory Window for $ \hbox{Ti/HfO}_{x}$ Pillar RRAM at 50-nm Scale by Optimal Encapsulation Layer

A scaling feasibility for the process integration of the Ti/HfO
_x
, resistance memory with pillar structure is studied in this letter. An empirical model is successfully developed to correlate the forming voltage of devices to their cell sizes. The abnormal increase in the breakdown voltage and the absence of the resistance switching characteristic for the scaled devices (<; 150 nm) are observed for the devices encapsulated with the SiO
₂
film. This result is attributed to the reduction in the oxy gen-gettering ability of the Ti top layer by the SiO
₂
passivation layer. For scaled devices with the Si
₃
N
₄
passivation layer, the Ti film retains the same oxygen-gettering ability as the large devices. A 0.5-V reduction in the forming voltage for the 50-nm devices by using the S
₃
N
₄
, instead of the SiO
₂
, layer is observed. The 50-nm devices with the Si
₃
N
₄
encapsulating layer exhibits improved memory performances such as large on/off ratio (>; 100), high temperature stability at 200 °C for 500 min, and satisfactory endurance (10
⁴
cycles).