Through-wafer via modeling based on direct RF characterization

This paper presents a methodology for determining the series resistance of (through-wafer interconnect) Vias directly from measured S-Parameters using an ultra-low impedance measurement known as the “S21-Shunt” technique. Data is acquired following on-wafer SOLT calibration using standard VNA / PNA hardware by characterizing “series-shunt” configured test structures. Measurement errors attributable to probe contact resistance (PCR) and its associated variability are eliminated through application of the presented methodology. Parameters associated with a lumped-element equivalent-circuit (LE-EC) based model are determined via direct extraction using slope and intercept methods. A parametric sub-circuit model, which incorporates frequency-dependent elements and exhibits statistical predictability has been implemented in the (ADS) design kit / PDK environment. The model is generated directly from measured data by automating the data acquisition and post processing sequences under a comprehensive test executive platform (such as ACE or ACSRF).