Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy) and aluminum pad. The purpose of this study is to measure and calculate thermally-induced deformations and stresses of flip-chip ball grid array (BGA) packages with a copper-pillar-bump interconnected chip inside. In the experiments, full-field Twyman-Green and moire interferometries are used to measure out-of-plane deformations on the chip surfaces of the package during a heating process and in-plane deformations on the cross-section surface of the package under a specific thermal loading, respectively. A finite element method (FEM) and Suhir's die-attachment assembly theory being validated by experimental data are employed to analyze the thermally-induced deformations and stresses of the package to gain insight into their mechanics. The experimental results show the zero-warpage temperature (or zero-stress temperatures) for this package is 115°C due to the Tg of the underfill material rather than its curing temperature. It is also found that the thermal deformations of the package calculated by FEM and theory are well consistent with Twyman-Green and moire results. Furthermore, the local stresses around the critical copper-pillar bump joint region (especially at aluminum pad and low-k layer) where the possible failures occur during the TCT are investigated in detail through the validated FEM model. The results indicate that die/substrate thickness ratio would have significant effect on the stresses at aluminum pad and low-k layer, as well as package warpage and die stress.