Design and test of latch-based circuits to maximize performance, yield, and delay test quality

The performance benefits of latch-based circuits have been known for some time. These benefits are due to the timing flexibility and skew-tolerance enabled by the ability of combinational logic blocks to borrow time from each other across the intervening level-sensitive latches. It has also been known that, by accommodating higher levels of process variations and small delay-defects, time borrowing can enhance yield at high clock frequencies. The main roadblock was that conventional scan-based delay testing approaches cannot be adapted from flip-flop-based (FF-based) circuits to latch-based circuits in a manner that can harvest above benefits. Recently, a scan-based delay testing approach has been proposed for latch-based circuits which holds the promise of harvesting the abovementioned performance and yield benefits. In this paper, we investigate two main questions. First, can this new scan-based delay testing approach provide high coverage of delay faults for all latch-based circuits - independent of the pervasiveness of time borrowing? Second, how do we design the circuit and develop tests so as to harvest maximal performance and yield benefits? We prove that the above delay testing approach for latch-based circuits obtains the maximum path delay fault coverage possible for any scan-based test methodology and this test quality is always greater than (or equal to) that obtainable for the corresponding FF-based circuit. We derive the conditions to satisfy during design and test development to guarantee maximal performance and yield benefits of latch-based designs vs. their FF-based counterparts. Hence, we show for the first time that it is possible for latch-based circuits to provide higher performance and yield and also to certify the higher performance via high delay test quality.