Improvement of threshold voltage shift distribution characteristic in double layer NiSi2 nanocrystals for nano-floating gate memory applications

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si
₃
N
₄
interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO
₂
interlayer, the use of Si
₃
N
₄
interlayer dielectric reduced the average size (4 nm) and distribution (2.5 nm) of NiSi
₂
nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 × 10
¹²
cm
^-2
. The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V, demonstrating possible multi-level-cell operation.