Pruning the Design Space for Just-in-Time Processor Customization

In this paper we study the feasibility of instruction set specialization for reconfigurable ASIPs at runtime. Applying known instruction set extension algorithms for static ASIPs in this just-in-time CPU specialization context is generally possible. However, the leading state-of-the-art algorithms for this purpose have an exponential algorithmic complexity which is prohibitive when targeting large applications and when the runtime of the customization process is a concern. Hence, we propose effective ways of pruning the design space which can reduce the runtime of instruction set extension algorithms by two orders of magnitude. We evaluate the proposed methods and our tool flow targeting the Wool Cano reconfigurable ASIP architecture with a comprehensive set of applications from the SPEC2006, SciMark2, and MiBench benchmark suites. For some applications we show a 44-fold speedup over a fixed CPU architecture. Finally, we elaborate why linear complexity instruction set extension algorithms are most suitable for just-in-time ASIP specialization.