A hardware architecture of Prewitt edge detection

This paper presents an efficient hardware architecture of Prewitt edge detection for high speed image processing applications. The hardware design is implemented by using Verilog hardware description language, whereas the software part is developed by using Matlab. The zero computational error analysis indicates that the proposed architecture produces similar outputs with ideal result obtained by Matlab software simulation. The architecture is capable of operating at a clock frequency of 145 MHz at 550 frames per second (fps), which implies that the system is suitable for both image processing and computer vision applications.