A power-gatable reconfigurable logic chip with FeRAM cells

An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using SRAM as a configuration memory. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead - data hibernation and reconfiguration time - and SRAM being volatile. In this paper, we describe a chip that we developed - a reconfigurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible. The hibernate/restore time is less than I ms. The chip has 18 × 18 logic blocks and an area of 54.76 mm
²
. We also make test circuits for testing the chip after fabrication. Target fault model is Stack-at faults model. When we merge all 28 circuits, fault coverage is 78%.