A novel hierarchical test generation method for processors

This paper describes a novel method for hierarchical functional test generation for processors. This method targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Since the commercial tools are unable to deal with the entire design, functional constraints are first extracted for the module. The extracted constraints are described in Verilog/VHDL and synthesized to the gate level. Then a commercial sequential ATPG is used to generate module level test vectors for faults within the module. Finally, these module level vectors are translated to processor level functional vectors and fault simulated to verify that the same coverage is obtained. Applying the technique to a benchmark processor design, we were able to obtain a test efficiency for the embedded ALU of the processor which was extremely close to what the commercial ATPG could do with complete access to the module.