Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems

The partial reconfigurability of FPGAs allows real-time systems to adapt to changing application requirements. However, the additional time and power needed for partial reconfiguration as well as the sequential reconfiguration process degrade the overall system performance. This is considered as one of the main reasons for restricted use of partial reconfiguration technology. In addition, hardware interrupts have not been well supported in existing systems, which makes the task preemption hard to realize in real-time systems. In this paper, we will propose a novel mechanism for reusing already configured hardware and a generic interrupt handling mechanism. Experimental results show that when our reuse mechanism could be applied, a reduction of approximately 1400x in terms of loaded configuration data can be achieved compared to the traditional reconfiguration. Our interrupt mechanism brings additional flexibility and has up to two orders of magnitude less interrupt overhead compared to the widely used read back mechanism.